A memory device, such as dynamic random-access memory (DRAM), can include memory cells. Each memory cell can typically store one bit of information by holding or not holding a charge in, for example, a capacitor. The presence or absence of a charge indicates, for example, logic 1 when a charge is stored, and logic 0 when no charge is stored. Electrical disturbance, such as interference from noise or radiation, can change the contents of one or more memory cells or interfere with the circuitry used to read and write data to the memory cells. Furthermore, memory devices are being designed to operate at increasingly higher throughput rates and lower power consumption, which can lead to increasingly higher bit error rates. A bit error can cause corruption of data, security vulnerabilities, or a system crash.
Error correcting code (ECC) can be used to detect and correct bit errors. ECC encodes data by generating ECC data, e.g., redundancy bits or parity bits, that are stored along with the data in a memory device. For example, 8 parity bits can be generated for 32 bits of data or 64 bits of data. An ECC that generates 8 bits of parity for 32 bits of data can usually detect two bit errors and correct one bit error in the 32 bits of data. Similarly, an ECC that generates 8 parity bits for 64 bits of data can usually detect two bit errors and correct one bit error in the 64 bits of data.
Typically, an ECC memory device is used in a system to provide ECC capability. An ECC memory device can include an extra memory chip that is designated for storing ECC information. An ECC memory device can also include an interface that can provide simultaneous access of a data word and its corresponding ECC information. For example, an ECC memory device that can provide 8-bit parity for each 32-bit data word may include a 40-bit wide interface to access a 32-bit data word. Similarly, an ECC memory device that can provide 8-bit parity for each 64-bit data word may include a 72-bit wide interface to access a 64-bit data word.
However, a consumer may desire stronger ECC protection than the ECC protection provided by an ECC memory device. Traditional ECC systems typically provide limited ECC capability because such systems generate and store limited ECC information. For example, a 72-bit ECC memory supports 8-bit parity for a 64-bit data word, which typically provides 1-bit error correction and 2-bit error detection. Traditional ECC systems typically cannot provide ECC capability with two or more bit error correction, which may be needed to protect critical system data when a memory is operating at a very high data rate.
Additionally, a consumer may choose to use a system that does not support an ECC memory device, but may still desire ECC capability. A system that supports an ECC memory device may be associated with higher costs than a system that does not support an ECC memory device. For example, system components, such as motherboards, chipsets, and processors, that support ECC memory devices may be more expensive than system components that do not support ECC memory devices. Even when a system supports an ECC memory device, a consumer may choose to use a non-ECC memory device, but still desire ECC capability. An ECC memory device may be more expensive than a non-ECC memory device because of the extra memory chip and wider interface provided by the ECC memory device to implement ECC functionality.